Reductions in the thickness (i.e., Z-height) of semiconductor packages are largely the result of thinner substrates and dies. However, as the substrates and dies continue to shrink in thickness, the amount of warpage increases. The warpage is inherently caused by the coefficient of thermal expansion (CTE) mismatch between the substrate and the die. For example, a typical package substrate may have a CTE of approximately 20 ppm, whereas the CTE of a silicon die is approximately 3.0 ppm.
Semiconductor dies are packaged with a package assembly process. To increase throughput, a plurality of dies may be packaged on a single panel. The panel may then be diced into individual packages, each of which may include a single die. Excess warpage is a significant contributor to multiple assembly issues at both the panel level and after the package has been singulated. As such, if warpage is not adequately controlled, then the package assembly process may have a poor yield. For example, warpage of the package may increase the risk that surface mount technology (SMT) will not be able to reliably mount the package to a printed circuit board (PCB). Therefore, warpage control is needed throughout the entire semiconductor die package assembly process.
For example, losses in yield and reductions in throughput may occur when a warped panel cannot be loaded properly into a processing tool or a panel carrier because the panel loading and unloading equipment are not be able to handle the warped panel. Also, a warped panel makes processes that rely on a depth of focus unreliable. For example, markings made on the panel with a laser may be incorrect because the warped surface causes some regions of the panel to be out of focus. Additionally, panel readers that check strip identification marks may not be able to accurately read an identification mark that is located on a portion of the panel that is warped. Furthermore, when warpage is present, attachment issues may occur. For example, solder bridging, non-contact opens (NCO), and ball attach issues may be caused by warped packages. Additionally, warpage may increase the difficulty of aligning testing pins.
Several methods to control warpage have been used, but each includes significant drawbacks. In cored packages, metal stiffeners have been attached to the die-side surface of the core. Adding a metal stiffener increases the Z-height of the package and adds additional processing operations which reduce throughput and increase cost. In coreless packages, such as bumpless build-up layer (BBUL) packaging, a cavity copper foil architecture has been utilized. However, such packages may require six or more additional processing operations.
FIGS. 1A-1E are illustrations of a process utilizing cavity copper foil architecture. First, in FIG. 1A, an etchstop layer 101 is formed over the surfaces of the BBUL core 102, and a copper foil layer 103 is laminated over the etchstop layers 101. An etchstop layer 101 is needed when a cavity copper foil architecture is used in order to prevent the core from being etched away during the formation of the cavity. Then in FIG. 1B, a dry film resist (DFR) layer 104 is laminated over the copper foil layer 103. The DFR layer 104 is then patterned with exposure and DFR etching processes, as shown in FIG. 1C. Referring now to FIG. 1D, the exposed copper foil 103 is etched away to form a cavity 120. After the cavity 120 is formed, the DFR film 104 may be stripped. Finally, a die 130 may be mounted to the etchstop layer 101 and a dielectric layer 105 may be laminated over the top surfaces of the die 130 and the copper foil 103, as shown in FIG. 1E. Accordingly, the additional processing operations needed for cavity copper foil architecture severely reduces throughput and increases the cost of production.